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A parallel FET linearizer with complex capacitance

✍ Scribed by Wai Keung Lo; Wing Shing Chan; Chung Wai Li

Publisher
John Wiley and Sons
Year
2005
Tongue
English
Weight
74 KB
Volume
44
Category
Article
ISSN
0895-2477

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✦ Synopsis

Linearization of the gate-source capacitance in a GaAs FET using a parallel reverse biased gate-source junction and complex capacitance is proposed. This method offers a simple and low-cost solution in reducing AM/PM distortion. An analysis for maximizing the performance of this linearizer is also presented.

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