This paper proposes a parallel approach to global routing using an associative processor (AP). The proposed architecture, which is very efficient for search-oriented applications, consists of three main functional blocks: the content-addressable memory (CAM) array, the row logic, and the control section. The proposed AP is a single instruction multiple data device based on a CAM core and an array of high-speed processors. With the parallel processing capabilities of the AP, we can utilize thousands of processing elements. As an application, we present a parallel algorithm to solve the global routing problem in the layout process utilizing the processing capabilities of the rudimentary logic and the selective matching and writing capability of CAMs, along with basic algorithms such as minimum (maximum) search, less-(greater-) than search, and parallel arithmetic. We have focused on the simultaneous minimization of the density of channels and of the wire length. The motivation for the proposed algorithm is to seek a less crowded channel with shorter wire distance by considering all possible paths in parallel under a given situation. An efficient algorithm with O(d) complexity for searching a minimum-weight path (where d is the number of nodes) is developed to find a shorter path through a less crowded channel. Experimental results on difficult examples, on randomly generated data, and on benchmark problems from the Physical Design Workshop are included.