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A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

✍ Scribed by M. Olivieri; G. Scotti; A. Trifiletti


Book ID
126749196
Publisher
IEEE
Year
2005
Tongue
English
Weight
637 KB
Volume
13
Category
Article
ISSN
1063-8210

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