A solenoidal structure for implementation of on-chip inductors is presented. An electromagnetic simulator is used to simulate several different-size inductors for up to 20 GHz. Additionally, artificial neural network models are developed for different inductor topologies to speed up inductors optimi
A new geometrical optimization technique for RF integrated inductors
β Scribed by H. P. Tan; K. S. Yeo; J. G. Ma; M. A. Do
- Publisher
- John Wiley and Sons
- Year
- 2000
- Tongue
- English
- Weight
- 104 KB
- Volume
- 26
- Category
- Article
- ISSN
- 0895-2477
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β¦ Synopsis
This letter describes a new approach to maximize the ( ) quality Q factor of a spiral inductor without any modifications to the existing CMOS or BiCMOS processes. The proposed method is based on successi¨ely increasing the metal width from the inner to the outer turns of the spiral inductor. This method has been used to realize an optimized inductor for RF applications. The comparati¨e e¨aluation shows that the optimized inductor outperforms four other spiral inductors with fixed metal widths of 10, 15, 20, and 25 in terms of the Q-factor without sacrificing the inductance and chip area.
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