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A new framework of design rules for compaction of VLSI layouts

โœ Scribed by Jin-Fuw Lee


Book ID
119778769
Publisher
IEEE
Year
1988
Tongue
English
Weight
980 KB
Volume
7
Category
Article
ISSN
0278-0070

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An efficient geometrical design rule checker is proposed, based on operations on quadtrees, which represent VLSI mask layouts. The time complexity of the design rule checker is O(N.), where N is the number of polygons in the mask. A pseudoPascal description is provided of all the important algorithm