A multiprocessor system architecture suited for power system transient calculation

✍ Scribed by Masato Yamamoto; Toshiyuki Nakata; Yoitsu Kurita

• Publisher: John Wiley and Sons
• Year: 1999
• Tongue: English
• Weight: 180 KB
• Volume: 128
• Category: Article
• ISSN: 0424-7760
• DOI: 10.1002/(sici)1520-6416(19990715)128:1<26::aid-eej4>3.0.co;2-e

✦ Synopsis

In the field of power system calculation, much research has been devoted to using parallel computers to increase computation speed. However, unlike examples in other application areas, such as circuit simulation or computational fluid dynamics, the performance gain is small. Also, the performance gain begins to saturate after a small number of processors are utilized. This is due to the essential features of power system calculation: mainly, (1) the size of the problem is usually much smaller than in other application fields and (2) the sparsity of the problem is high. These two features amplify the effect of interprocessor communication overhead.

In this study, the authors sought the most suitable parallel architecture for power system calculation, restricting the number of processors to about 16. The architectural features of interest are the memory architecture and the interprocessor connection method. The candidates chosen are: (1) distributed memory architecture connected by an interprocessor communication network, (2) distributed memory architecture connected by a bus, (3) shared memory architecture connected by a bus, and (4) composite distributed/shared memory architecture connected by a bus. We evaluate each architecture in terms of the data for transient stability analysis from a single PE execution, with consideration of memory operations, necessary interprocessor communication, and computations. The results show that although little increase in speed is gained by using a distributed shared memory architecture connected by an interconnection network, it is possible to attain a speedup by a factor of 6.5 by using 16 PEs on a composite distributed/shared memory architecture connected by a bus.