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A method for multiple-level logic synthesis based on the simulated annealing algorithm

✍ Scribed by Juan Lanchares; JoséIgnacio Hidalgo; Juan Manuel Sánchez

Book ID: 108361538
Publisher: Elsevier Science
Year: 1997
Tongue: English
Weight: 560 KB
Volume: 28
Category: Article
ISSN: 0026-2692
DOI: 10.1016/s0026-2692(96)00063-8

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