A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III–V MOSFETs

✍ Scribed by X. Li; R.J.W. Hill; H. Zhou; C.D.W. Wilkinson; I.G. Thayne

• Book ID: 104051877
• Publisher: Elsevier Science
• Year: 2008
• Tongue: English
• Weight: 345 KB
• Volume: 85
• Category: Article
• ISSN: 0167-9317
• DOI: 10.1016/j.mee.2007.12.064