Recent research in knowledge-based expert systems k)r VLSI tools" design has concentrated on floor-planning, placement, routing, and (:ell generation. The paper describes a knowledge-based scanning-line approach to VLSI layout compaction. This approach differs Jrom traditional algorithmic approaches: an expert compactor interprets constraints by production rules in a more 'intelligent" way. Experimental results show that the presented system can compete with conventional algorithmic approaches. compuler aided design, knowledge-based system, VLSI-CAD tools, layout ( ompacti~n Like most of the VLSI-CAD tools' design, layout compaction is characterized as having a large problemspace. Some algorithmic approaches have already accomplished a practical solution 72. However, the performance of algorithmic approaches ~4 is not comparable with most sophisticated human experts. In an attempt to apply artificial intelligence and expert system technology in the field of of VLSI-CAD tools' design, this paper concentrates on capturing compaction expertise into a knowledge-based expert system, which can then be compared with algorithmic compactors 14. Even though there were several expert systems published for layout verification ~, synthesis ~, placement 7, routing ".~' , cell generation"', floorplanning', and ASIC design ~2, the main idea for expert compaction was recently presented in Hsiao et al. ~ and Matsumoto. ~ This paper is an extension of Hsiao et al. ~ and the system is written in OPS5 language.
CONSTRAINT PRIMITIVE
Layout constraints are formed from the layout design rules, electrical requirements, and user-specified constraints. For most of the VLSI mask layout, the mask diagrams are generated by rectangles and rectilinear