✦ LIBER ✦
A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic
✍ Scribed by Lowe, K.S.; Gulak, P.G.
- Book ID
- 119778336
- Publisher
- IEEE
- Year
- 1998
- Tongue
- English
- Weight
- 502 KB
- Volume
- 17
- Category
- Article
- ISSN
- 0278-0070
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