A Hysteresis-Based D-Flip-Flop Design in 28 nm CMOS for Improved SER Hardness at Low Performance Overhead

✍ Scribed by Narasimham, B.; Chandrasekharan, K.; Liu, Z.; Wang, J. K.; Djaja, G.; Gaspard, N. J.; Kauppila, J. S.; Bhuva, B. L.

• Book ID: 120081117
• Publisher: IEEE
• Year: 2012
• Tongue: English
• Weight: 666 KB
• Volume: 59
• Category: Article
• ISSN: 0018-9499
• DOI: 10.1109/TNS.2012.2223762