✦ LIBER ✦

A heuristic procedure for makespan minimization in job shops with multiple identical processors

✍ Scribed by Dileep R. Sule; Karthick Vijayasundaram

Publisher: Elsevier Science
Year: 1998
Tongue: English
Weight: 364 KB
Volume: 35
Category: Article
ISSN: 0360-8352
DOI: 10.1016/s0360-8352(98)00118-1

No coin nor oath required. For personal study only.

✦ Synopsis

Scheduling has been and continues to be a major issue in production planning. Job shop scheduling is one area where a considerable amount of research has been and continues to be pursued. Usual emphasis is on one machine per work center job shop scheduling. There appears to be very limited literature available on scheduling a job shop problem which requires scheduling of n jobs in m machine centers where each machine center may have k number of identical processors (though the number of identical processors may vary from one machine center to next). We discuss here, the problem of minimize of the makespan for such a job shop arrangement The problem can be represented by the symbol m x n x k.

📜 SIMILAR VOLUMES

A shifting bottleneck heuristic for mini

A shifting bottleneck heuristic for minimizing the total weighted tardiness in a job shop

✍ Michael Pinedo; Marcos Singer 📂 Article 📅 1999 🏛 John Wiley and Sons 🌐 English ⚖ 165 KB 👁 2 views

We present a shifting bottleneck heuristic for minimizing the total weighted tardiness in a job shop. The method decomposes the job shop into a number of single-machine subproblems that are solved one after another. Each machine is scheduled according to the solution of its corresponding subproblem.

A modified shifting bottleneck heuristic

A modified shifting bottleneck heuristic for minimizing total weighted tardiness in complex job shops

✍ Scott J. Mason; John W. Fowler; W. Matthew Carlyle 📂 Article 📅 2002 🏛 Springer US 🌐 English ⚖ 138 KB

Increases in the demand for integrated circuits have highlighted the importance of meeting customer quality and on-time delivery expectations in the semiconductor industry. A modiÿed shifting bottleneck heuristic is developed for minimizing the total weighted tardiness in a semiconductor wafer fabri