A heterogeneous computer vision architecture: Implementation issues

✍ Scribed by Henrique Dinis Santos; JoséCarlos Ramalho; João Miguel Fernandes; Alberto José Proença

• Book ID: 103975152
• Publisher: Elsevier Science
• Year: 1995
• Weight: 690 KB
• Volume: 6
• Category: Article
• ISSN: 0956-0521
• DOI: 10.1016/0956-0521(95)00029-1

✦ Synopsis

The prototype of a heterogeneous architecture is currently being built. The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level--transputer based--and on VLSI associative processor arrays (APA, SIMD structure) for low level image processing tasks. The APA structure is implemented through a set of 4 VLSI chips (GLITCH) containing 64 1-bit processing elements each. This communication addresses some issues concerning the implementation of the first prototype, namely those related to:

--the design and integration of the APA controller unit, which provides the required interface between the APA, the MIMD topology and the video image interface:

the evaluation of the GLITCH chip through an emulator based on transputers and fast programmable devices; the emulator was designed to be flexible enough to evaluate later modifications to the GLITCH design;

--the design of an integrated set of software development tools containing a structured editor--syntax oriented, with a visual interface/programming interface--and a cross compiler and debugger.