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A Gated Clock Scheme for Low Power Testing of Logic Cores

✍ Scribed by Yannick Bonhomme; Patrick Girard; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel

Publisher
Springer US
Year
2006
Tongue
English
Weight
289 KB
Volume
22
Category
Article
ISSN
0923-8174

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