A fast method for timing verification that uses the conditions that cause changes in the output values of gates

✍ Scribed by Atsushi Ohnishi; Yuji Sugiyama

• Publisher: John Wiley and Sons
• Year: 2000
• Tongue: English
• Weight: 152 KB
• Volume: 32
• Category: Article
• ISSN: 0882-1666
• DOI: 10.1002/1520-684x(200101)32:1<38::aid-scj5>3.0.co;2-f