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A fail-safe realization of alternating logic : H. Yamamoto, Y. Urano and T. Watanabe. Trans. Inst. Electron. Commun. Engrs Japan 54-C, No. 12 (1971), p. 1079, (In Japanese)

Publisher: Elsevier Science
Year: 1972
Tongue: English
Weight: 104 KB
Volume: 11
Category: Article
ISSN: 0026-2714
DOI: 10.1016/0026-2714(72)90494-5

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