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A discrete-time queueing model of the shared buffer ATM switch with bursty arrivals

โœ Scribed by S. Hong; H. G. Perros; H. Yamashita


Publisher
Springer US
Year
1993
Tongue
English
Weight
934 KB
Volume
2
Category
Article
ISSN
1018-4864

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A model for the analysis of multistage switches based on shared bu!er switching for Asynchronous Transfer Mode (ATM) networks is developed, and the results are compared with the simulation. Switches constructed from shared bu!er switches do not su!er from the head of line blocking which is the commo