A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit

✍ Scribed by Kuo, J.B.; Su, K.W.; Lou, J.H.

• Book ID: 119774373
• Publisher: IEEE
• Year: 1995
• Tongue: English
• Weight: 392 KB
• Volume: 30
• Category: Article
• ISSN: 0018-9200
• DOI: 10.1109/4.400440