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A 60-ns 16-Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance

✍ Scribed by Chou, S.; Takano, T.; Kita, A.; Ichikawa, F.; Uesugi, M.


Book ID
119798793
Publisher
IEEE
Year
1989
Tongue
English
Weight
865 KB
Volume
24
Category
Article
ISSN
0018-9200

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