A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique

✍ Scribed by Ye, Y.; Khellah, M.; Somasekhar, D.; Farhang, A.; De, V.

• Book ID: 119799120
• Publisher: IEEE
• Year: 2003
• Tongue: English
• Weight: 717 KB
• Volume: 38
• Category: Article
• ISSN: 0018-9200
• DOI: 10.1109/jssc.2003.810057