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A 32-Mb chain FeRAM with segment/stitch array architecture

✍ Scribed by Shiratake, S.; Miyakawa, T.; Takeuchi, Y.; Ogiwara, R.; Kamoshida, M.; Hoya, K.; Oikawa, K.; Ozaki, T.; Kunishima, I.; Yamakawa, K.; Sugimoto, S.; Takashima, D.; Joachim, H.-O.; Rehm, N.; Wohlfahrt, J.; Nagel, N.; Beitel, G.; Jacob, M.; Roehr, T.

Book ID: 119799230
Publisher: IEEE
Year: 2003
Tongue: English
Weight: 962 KB
Volume: 38
Category: Article
ISSN: 0018-9200
DOI: 10.1109/jssc.2003.818161

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