A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism

✍ Scribed by Kubosawa, H.; Higaki, N.; Ando, S.; Takahashi, H.; Asada, Y.; Anbutsu, H.; Sato, T.; Sakate, M.; Suga, A.; Kimura, M.; Miyake, H.; Okano, H.; Asato, A.; Kimura, Y.; Nakayama, H.; Kimoto, M.; Hirochi, K.; Saito, H.; Kaido, N.; Nakagawa, Y.; Shimada, T.

• Book ID: 119775475
• Publisher: IEEE
• Year: 1999
• Tongue: English
• Weight: 994 KB
• Volume: 34
• Category: Article
• ISSN: 0018-9200
• DOI: 10.1109/4.799871