✦ LIBER ✦
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency
✍ Scribed by Heald, R.; Shin, K.; Reddy, V.; I-Feng Kao; Khan, M.; Lynch, W.L.; Lauterbach, G.; Petolino, J.
- Book ID
- 119775167
- Publisher
- IEEE
- Year
- 1998
- Tongue
- English
- Weight
- 186 KB
- Volume
- 33
- Category
- Article
- ISSN
- 0018-9200
- DOI
- 10.1109/4.726558
No coin nor oath required. For personal study only.