60-GHz CMOS Phase-Locked Loops
β Scribed by Hammad M. Cheema, Reza Mahmoudi, Arthur H. M. Roermund (auth.)
- Publisher
- Springer Netherlands
- Year
- 2010
- Tongue
- English
- Leaves
- 206
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
β¦ Synopsis
The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market.
60-GHz CMOS Phase-Locked Loops focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of individual components such as voltage controlled oscillators, injection locked frequency dividers and their combinations, are included. Furthermore, to satisfy a number of transceiver topologies simultaneously, flexibility is introduced in the PLL architecture by using new dual-mode ILFDs and switchable VCOs, while reusing the low frequency components at the same time.β¦ Table of Contents
Front Matter....Pages i-viii
Introduction....Pages 1-9
Synthesizer System Architecture....Pages 11-34
Layout and Measurements at mm-Wave Frequencies....Pages 35-55
Design of High Frequency Components....Pages 57-149
Design of Low Frequency Components....Pages 151-164
Synthesizer Integration....Pages 165-181
Conclusions....Pages 183-184
Back Matter....Pages 185-197
β¦ Subjects
Circuits and Systems; Microwaves, RF and Optical Engineering; Solid State Physics
π SIMILAR VOLUMES
<p>This book is devoted to a detailed and comprehensive study of phase locked loops aimed at preparing the reader to design them and to understand their applications. It is written at a level corresponding to a final year electronics undergraduate or a postgraduate student. Linear and semidigital ph
Engineers face stiff challenges in designing phase-locked loop (PLL) circuits for wireless communications thanks to phase noise and other obstacles. This practical book comes to the rescue with a proven PLL design and optimization methodology that lets designers assess their options, predict PLL beh