✦ LIBER ✦
250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture
✍ Scribed by Takai, Y.; Nagase, M.; Kitamura, M.; Koshikawa, Y.; Yoshida, N.; Kobayashi, Y.; Obara, T.; Fukuzo, Y.; Watanabe, H.
- Book ID
- 119773978
- Publisher
- IEEE
- Year
- 1994
- Tongue
- English
- Weight
- 518 KB
- Volume
- 29
- Category
- Article
- ISSN
- 0018-9200
- DOI
- 10.1109/4.280691
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